As speeds and complexity of devices such as memory devices, have increased, so has the frequency at which data is provided to and received from these devices. Various methodologies have been used to accomplish this, including high speed serial communication using, for example, the serial peripheral interface (SPI) protocol. While high speed serial communication has been successful in allowing for higher data transmission frequencies, the increased frequencies have decreased the width of the “data eye” of data signals. That is, the amount of time in which a particular bit of a signal is available to be captured by a device is diminished. This in turn reduces tolerances for capturing data, and data transmission may be more prone to errors as a result.
To account for this, several different approaches have been utilized. One such approach comprises the use of strobe signals, wherein signals are provided in parallel with data, indicating to a device when each bit of the data should be captured. Some implementations do not use strobe signals, however, as the extra signal may be infeasible for a particular design. Thus, some designs may instead rely on calibration of device timings. That is, a device capturing data from a bus may be calibrated to capture data at specific times relative to a signal, such as a clock signal. This approach may incur its own set of challenges, however, as calibrations may not be effective for varying operating conditions, and/or may not configure a device for accurate detection of all possible data patterns.